1. Field of Invention
The present invention pertains to the field of digital systems. More particularly, this invention relates to reducing the hardware costs of a bank of multipliers.
2. Art Background
A wide variety of digital systems commonly include banks of multipliers which serve a variety of functions. For example, a digital filter commonly includes a bank of multipliers which is used to multiply a filter input signal by a set of filter coefficients. In addition, fast Fourier transform (FFT) circuits, discrete Fourier transform (DFT) circuits, and image processing circuits commonly include banks of multipliers.
Typically, each multiplier in a bank of multipliers is implemented with a set of adders. In the case of a digital filter, the number of adders needed for a multiplier is usually equal to the number of "one" bits in the corresponding filter coefficient if the filter coefficients are constant.
It is usually desirable in a digital system to minimize the number of adders needed to implement a bank of multipliers. A reduction in the number of adders typically reduces the integrated circuit space required to implement the bank of multipliers and thereby reduces the overall cost and complexity of the digital system.